? semiconductor components industries, llc, 2006 july, 2006 ? rev. 6 1 publication order number: SN74LS290/d SN74LS290 decade counter; 4-bit binary counter the sn54/74ls290 and sn54/74ls293 are high-speed 4-bit ripple type counters partitioned into two sections. each counter has a divide-by-two section and either a divide-by-five (ls290) or divide-by-eight (ls293) section which are triggered by a high-to-low transition on the clock inputs. each section can be used separately or tied together (q to cp )to form bcd, bi-quinary, or modulo-16 counters. both of the counters have a 2-input gated master reset (clear), and the ls290 also has a 2-input gated master set (preset 9). ? corner power pin versions of the ls90 and ls93 ? low power consumption . . . typically 45 mw ? high count rates . . . typically 42 mhz ? choice of counting modes . . . bcd, bi-quinary, binary ? input clamp diodes limit high speed termination effects 14 13 12 11 10 9 123456 8 7 v cc mr mr cp 1 cp 0 q 0 q 3 ms nc ms q 2 q 1 nc gnd connection diagram dip (top view) ls290 ls293 note: the flatpak version has the same pinouts (connection diagram) as the dual in-line pack- age. 14 13 12 11 10 9 123456 8 7 v cc mr mr cp 1 cp 0 q 0 q 3 nc nc nc q 2 q 1 nc gnd pin names loading (note a) high low cp 0 clock (active low going edge) input to 2 section. 0.05 u.l. 1.5 u.l. cp 1 clock (active low going edge) input to 5 section (ls290). 0.05 u.l. 2.0 u.l. cp 1 clock (active low going edge) input to 8 section (ls293). 0.05 u.l. 1.0 u.l. mr1, mr2 master reset (clear) inputs 0.5 u.l. 0.25 u.l. ms1, ms2 master set (preset-9, ls290) inputs 0.5 u.l. 0.25 u.l. q0 output from 2 section (notes b & c) 10 u.l. 5 (2.5) u.l. q1, q2, q3 outputs from 5 & 8 sections (note b) 10 u.l. 5 (2.5) u.l. notes: a) 1 ttl unit load (u.l.) = 40 a high/1.6 ma low. b) the output low drive factor is 2.5 u.l. for military (54) and 5 u.l. for commercial (74) temperature ranges. c) the q 0 outputs are guaranteed to drive the full fan-out plus the cp 1 input of the device. http://onsemi.com decade counter; 4-bit binary counter low power schottky j suffix ceramic case 632-08 n suffix plastic case 646-06 14 1 14 1 14 1 d suffix soic case 751a-02 ordering information sn54lsxxxj ceramic sn74lsxxxn plastic sn74lsxxxd soic
SN74LS290 http://onsemi.com 2 logic symbol figure 1. ls290 figure 2. ls293 v cc = pin 14 gnd = pin 7 nc = pins 2, 6 13 12 12 10 11 ms cp 0 cp 1 mr q 0 q 1 q 2 q 3 12 13 9 5 4 8 v cc = pin 14 gnd = pin 7 nc = pins 1, 2, 3, 6 12 10 11 cp 0 cp 1 mr q 0 q 1 q 2 q 3 12 13 9 5 4 8 ls290 ls293 logic diagrams s d j cp c d q qj cp c d q qj cp c d q qr cp c d q q s d ks j cp c d q q k j cp c d q q k j cp c d q q k j cp c d q q k ms 1 ms 2 cp 0 cp 1 mr 1 mr 2 cp 0 cp 1 mr 1 mr 2 q 0 q 1 q 2 q 3 q 0 q 1 q 2 q 3 v cc = pin 14 gnd = pin 7 = pin numbers v cc = pin 14 gnd = pin 7 = pin numbers 1 3 8 4 5 9 11 12 10 13 10 13 11 12 8 4 5 9 k
SN74LS290 http://onsemi.com 3 functional description the ls290 and ls293 are 4-bit ripple type decade, and 4-bit binary counters respectively. each device consists of four master / slave flip-flops which are internally connected to provide a divide-by-two section and a divide-by-five (ls290) or divide-by-eight (ls293) section. each section has a separate clock input which initiates state changes of the counter on the high- to-low clock transition. state changes of the q outputs do not occur simultaneously because of internal ripple delays. therefore, decoded output signals are subject to decoding spikes and should not be used for clocks or strobes. the q 0 output of each device is designed and specified to drive the rated fan-out plus the cp 1 input of the device. a gated and asynchronous master reset (mr 1 ? mr 2 ) is provided on both counters which overrides the clocks and resets (clears) all the flip-flops. a gated and asynchronous master set (ms 1 ? ms 2 ) is provided on the ls290 which overrides the clocks and the mr inputs and sets the outputs to nine (hllh). since the output from the divide-by-two section is not internally connected to the succeeding stages, the devices may be operated in various counting modes: ls290 a. bcd decade (8421) counter ? the cp 1 input must be externally connected to the q 0 output. the cp 0 input receives the incoming count and a bcd count sequence is produced. b. symmetrical bi-quinary divide-by-ten counter ? the q 3 output must be externally connected to the cp 0 input. the input count is then applied to the cp 1 input and a divide-by-ten square wave is obtained at output q 0 . c. divide-by-two and divide-by-five counter ? no external interconnections are re quired. the first flip-flop is used as a binary element for the divide-by-two function (cp 0 as the input and q 0 as the output). the cp 1 input is used to obtain binary divide-by-five operation at the q 3 output. ls293 a. 4-bit ripple counter ? the output q 0 must be externally connected to input cp 1 . the input count pulses are applied to input cp 0 . simultaneous division of 2, 4, 8, and 16 are performed at the q 0 , q 1 , q 2 , and q 3 outputs as shown in the truth table. b. 3-bit ripple counter ? the input count pulses are applied to input cp 1 . simultaneous frequency divisions of 2, 4, and 8 are available at the q 1 , q 2, and q 3 outputs. independent use of the first flip-flop is available if the reset function coincides with reset of the 3-bit ripple-through counter. ls290 mode selection reset/set inputs outputs mr 1 mr 2 ms 1 ms 2 q 0 q 1 q 2 q 3 h h l x l l l l h h x l l ll l x x h h h ll h l x l x count x l x l count l x x l count x l l x count ls290 bcd count sequence count output q 0 q 1 q 2 q 3 0 l l l l 1 h ll l 2 l hl l 3 h hl l 4 l lh l 5 h lh l 6 l hh l 7 h hh l 8 l llh 9 h l l h note: output q 0 is connected to input cp 1 for bcd count. h = high voltage level l = low voltage level x = don?t care
SN74LS290 http://onsemi.com 4 ls293 mode selection reset inputs outputs mr 1 mr 2 q 0 q 1 q 2 q 3 h h l l l l l h count h l count l l count truth table count output q 0 q 1 q 2 q 3 0 l l l l 1 h ll l 2 l hl l 3 h hl l 4 l lh l 5 h lh l 6 l hh l 7 h hh l 8 l ll h 9 h ll h 10 l hl h 11 h hl h 12 l lh h 13 h lh h 14 l hh h 15 h h h h note: output q 0 connected to input cp 1 . guaranteed operating ranges symbol parameter min typ max unit v cc supply voltage 54 74 4.5 4.75 5.0 5.0 5.5 5.25 v t a operating ambient temperature range 54 74 ? 55 0 25 25 125 70 c i oh output current ? high 54, 74 ? 0.4 ma i ol output current ? low 54 74 4.0 8.0 ma
SN74LS290 http://onsemi.com 5 dc characteristics over operating temperature range (unless otherwise specified) symbol parameter limits unit test conditions min typ max v ih input high voltage 2.0 v guaranteed input high voltage for all inputs v il input low voltage 54 0.7 v guaranteed input low voltage for all inputs 74 0.8 v ik input clamp diode voltage ? 0.65 ? 1.5 v v cc = min, i in = ? 18 ma v oh output high voltage 54 2.5 3.5 v v cc = min, i oh = max, v in = v ih or v il per truth table 74 2.7 3.5 v v ol output low voltage 54, 74 0.25 0.4 v i ol = 4.0 ma v cc = v cc min, v in = v il or v ih per truth table 74 0.35 0.5 v i ol = 8.0 ma i ih input high current 20 a v cc = max, v in = 2.7 v 0.1 ma v cc = max, v in = 7.0 v i il input low current ms, mr cp 0 cp 1 (ls290) cp 1 (ls293) ? 0.4 ? 2.4 ? 3.2 ? 1.6 ma v cc = max, v in = 0.4 v i os short circuit current (note 1) ? 20 ? 100 ma v cc = max i cc power supply current 15 ma v cc = max note 1: not more than one outpu t should be shorted at a time, nor for more than 1 second.
SN74LS290 http://onsemi.com 6 ac characteristics (t a = 25 c, v cc = 5.0 v, c l = 15 pf) symbol parameter limits unit ls290 ls293 min typ max min typ max f max cp 0 input clock frequency 32 32 mhz f max cp 1 input clock frequency 16 16 mhz t plh t phl propagation delay, cp 0 input to q 0 output 10 12 16 18 10 12 16 18 ns t plh t phl cp 0 input to q 3 output 32 34 48 50 46 46 70 70 ns t plh t phl cp 1 input to q 1 output 10 14 16 21 10 14 16 21 ns t plh t phl cp 1 input to q 2 output 21 23 32 35 21 23 32 35 ns t plh t phl cp 1 input to q 3 output 21 23 32 35 34 34 51 51 ns t phl ms input to q 0 and q 3 outputs 20 30 ns t phl ms input to q 1 and q 2 outputs 26 40 ns t phl mr input to any output 26 40 26 40 ns ac setup requirements (t a = 25 c, v cc = 5.0 v) symbol parameter limits unit ls290 ls293 min max min max t w cp 0 pulse width 15 15 ns t w cp 1 pulse width 30 30 ns t w ms pulse width 15 ns t w mr pulse width 15 15 ns t rec recovery time mr to cp 25 25 ns recovery time (t rec ) is defined as the minimum time required between the end of the reset pulse and the clock transition form high-to-low in order to recognize and transfer high data to the q outputs. figure 1 *cp q 1.3 v 1.3 v 1.3 v 1.3 v t phl t plh figure 2 figure 3 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v mr & ms cp q t phl t plh ms cp q 0 q 3 (ls290) *the number of clock pulses required between the t phl and t plh measurements can be determined from the appropriate t ruth tables. ac waveforms t w t w t rec t w t rec
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